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Refactoring: Renamed RTLIL::Module::wires to wires_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
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4
passes/fsm/fsm_detect.cc
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@ -173,11 +173,11 @@ struct FsmDetectPass : public Pass {
}
}
for (auto &wire_it : module->wires)
for (auto &wire_it : module->wires_)
if (wire_it.second->port_id != 0)
sig_at_port.add(assign_map(RTLIL::SigSpec(wire_it.second)));
for (auto &wire_it : module->wires)
for (auto &wire_it : module->wires_)
if (design->selected(module, wire_it.second))
detect_fsm(wire_it.second);
}