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Refactoring: Renamed RTLIL::Module::wires to wires_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
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2
passes/cmds/stat.cc
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@ -69,7 +69,7 @@ namespace
STAT_INT_MEMBERS
#undef X
for (auto &it : mod->wires)
for (auto &it : mod->wires_)
{
if (!design->selected(mod, it.second))
continue;