mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 21:27:00 +00:00
Code Activity

Refactoring: Renamed RTLIL::Module::wires to wires_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
Download patch file Download diff file Expand all files Collapse all files

6
passes/cmds/splice.cc
View file

@ -149,7 +149,7 @@ struct SpliceWorker
driven_bits.push_back(RTLIL::State::Sm);
driven_bits.push_back(RTLIL::State::Sm);
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (it.second->port_input) {
RTLIL::SigSpec sig = sigmap(it.second);
driven_chunks.insert(sig);
@ -175,7 +175,7 @@ struct SpliceWorker
SigPool selected_bits;
if (!sel_by_cell)
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (design->selected(module, it.second))
selected_bits.add(sigmap(it.second));
@ -203,7 +203,7 @@ struct SpliceWorker
std::vector<std::pair<RTLIL::Wire*, RTLIL::SigSpec>> rework_wires;
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (!no_outputs && it.second->port_output) {
if (!design->selected(module, it.second))
continue;