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Refactoring: Renamed RTLIL::Module::wires to wires_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
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2
passes/cmds/setundef.cc
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@ -129,7 +129,7 @@ struct SetundefPass : public Pass {
SigMap sigmap(module);
SigPool undriven_signals;
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (!it.second->port_input)
undriven_signals.add(sigmap(it.second));