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Refactoring: Renamed RTLIL::Module::wires to wires_

This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions

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@ -111,7 +111,7 @@ struct SetattrPass : public Pass {
if (!design->selected(module))
continue;
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (design->selected(module, it.second))
do_setunset(it.second->attributes, setunset_list);