mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-23 22:33:41 +00:00
Code Activity

Refactoring: Renamed RTLIL::Module::wires to wires_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
Download patch file Download diff file Expand all files Collapse all files

2
passes/cmds/scc.cc
View file

@ -114,7 +114,7 @@ struct SccWorker
SigPool selectedSignals;
SigSet<RTLIL::Cell*> sigToNextCells;
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (design->selected(module, it.second))
selectedSignals.add(sigmap(RTLIL::SigSpec(it.second)));