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Refactoring: Renamed RTLIL::Module::wires to wires_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
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4
passes/cmds/delete.cc
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@ -79,7 +79,7 @@ struct DeletePass : public Pass {
RTLIL::Module *module = mod_it.second;
if (flag_input || flag_output) {
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (design->selected(module, it.second)) {
if (flag_input)
it.second->port_input = false;
@ -95,7 +95,7 @@ struct DeletePass : public Pass {
std::set<std::string> delete_procs;
std::set<std::string> delete_mems;
for (auto &it : module->wires)
for (auto &it : module->wires_)
if (design->selected(module, it.second))
delete_wires.insert(it.second);