Refactoring: Renamed RTLIL::Module::wires to wires_

passes/cmds/add.cc

@@ -28,8 +28,8 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
 
 	if (module->count_id(name) != 0)
 	{
-		if (module->wires.count(name) > 0)
-			wire = module->wires.at(name);
+		if (module->wires_.count(name) > 0)
+			wire = module->wires_.at(name);
 
 		if (wire != NULL && wire->width != width)
 			wire = NULL;
@@ -52,7 +52,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
 		wire->port_output = flag_output;
 
 		if (flag_input || flag_output) {
-			wire->port_id = module->wires.size();
+			wire->port_id = module->wires_.size();
 			module->fixup_ports();
 		}
 

passes/cmds/delete.cc

@@ -79,7 +79,7 @@ struct DeletePass : public Pass {
 			RTLIL::Module *module = mod_it.second;
 
 			if (flag_input || flag_output) {
-				for (auto &it : module->wires)
+				for (auto &it : module->wires_)
 					if (design->selected(module, it.second)) {
 						if (flag_input)
 							it.second->port_input = false;
@@ -95,7 +95,7 @@ struct DeletePass : public Pass {
 			std::set<std::string> delete_procs;
 			std::set<std::string> delete_mems;
 
-			for (auto &it : module->wires)
+			for (auto &it : module->wires_)
 				if (design->selected(module, it.second))
 					delete_wires.insert(it.second);
 

passes/cmds/rename.cc

@@ -29,7 +29,7 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std::
 	if (module->count_id(to_name))
 		log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name.c_str(), module->name.c_str());
 
-	for (auto &it : module->wires)
+	for (auto &it : module->wires_)
 		if (it.first == from_name) {
 			log("Renaming wire %s to %s in module %s.\n", log_id(it.second), log_id(to_name), log_id(module));
 			module->rename(it.second, to_name);
@@ -105,13 +105,13 @@ struct RenamePass : public Pass {
 					continue;
 
 				std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
-				for (auto &it : module->wires) {
+				for (auto &it : module->wires_) {
 					if (it.first[0] == '$' && design->selected(module, it.second))
 						do it.second->name = stringf("\\_%d_", counter++);
 						while (module->count_id(it.second->name) > 0);
 					new_wires[it.second->name] = it.second;
 				}
-				module->wires.swap(new_wires);
+				module->wires_.swap(new_wires);
 
 				std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
 				for (auto &it : module->cells) {
@@ -135,13 +135,13 @@ struct RenamePass : public Pass {
 					continue;
 
 				std::map<RTLIL::IdString, RTLIL::Wire*> new_wires;
-				for (auto &it : module->wires) {
+				for (auto &it : module->wires_) {
 					if (design->selected(module, it.second))
 						if (it.first[0] == '\\' && it.second->port_id == 0)
 							it.second->name = NEW_ID;
 					new_wires[it.second->name] = it.second;
 				}
-				module->wires.swap(new_wires);
+				module->wires_.swap(new_wires);
 
 				std::map<RTLIL::IdString, RTLIL::Cell*> new_cells;
 				for (auto &it : module->cells) {

passes/cmds/scc.cc

@@ -114,7 +114,7 @@ struct SccWorker
 		SigPool selectedSignals;
 		SigSet<RTLIL::Cell*> sigToNextCells;
 
-		for (auto &it : module->wires)
+		for (auto &it : module->wires_)
 			if (design->selected(module, it.second))
 				selectedSignals.add(sigmap(RTLIL::SigSpec(it.second)));
 

passes/cmds/select.cc

@@ -161,7 +161,7 @@ static void select_op_neg(RTLIL::Design *design, RTLIL::Selection &lhs)
 		}
 
 		RTLIL::Module *mod = mod_it.second;
-		for (auto &it : mod->wires)
+		for (auto &it : mod->wires_)
 			if (!lhs.selected_member(mod_it.first, it.first))
 				new_sel.selected_members[mod->name].insert(it.first);
 		for (auto &it : mod->memories)
@@ -215,11 +215,11 @@ static void select_op_alias(RTLIL::Design *design, RTLIL::Selection &lhs)
 		SigMap sigmap(mod_it.second);
 		SigPool selected_bits;
 
-		for (auto &it : mod_it.second->wires)
+		for (auto &it : mod_it.second->wires_)
 			if (lhs.selected_member(mod_it.first, it.first))
 				selected_bits.add(sigmap(it.second));
 
-		for (auto &it : mod_it.second->wires)
+		for (auto &it : mod_it.second->wires_)
 			if (!lhs.selected_member(mod_it.first, it.first) && selected_bits.check_any(sigmap(it.second)))
 				lhs.selected_members[mod_it.first].insert(it.first);
 	}
@@ -278,7 +278,7 @@ static void select_op_diff(RTLIL::Design *design, RTLIL::Selection &lhs, const R
 
 		if (lhs.selected_modules.count(mod->name) > 0)
 		{
-			for (auto &it : mod->wires)
+			for (auto &it : mod->wires_)
 				lhs.selected_members[mod->name].insert(it.first);
 			for (auto &it : mod->memories)
 				lhs.selected_members[mod->name].insert(it.first);
@@ -376,7 +376,7 @@ static int select_op_expand(RTLIL::Design *design, RTLIL::Selection &lhs, std::v
 		RTLIL::Module *mod = mod_it.second;
 		std::set<RTLIL::Wire*> selected_wires;
 
-		for (auto &it : mod->wires)
+		for (auto &it : mod->wires_)
 			if (lhs.selected_member(mod_it.first, it.first) && limits.count(it.first) == 0)
 				selected_wires.insert(it.second);
 
@@ -700,22 +700,22 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
 
 		RTLIL::Module *mod = mod_it.second;
 		if (arg_memb.substr(0, 2) == "w:") {
-			for (auto &it : mod->wires)
+			for (auto &it : mod->wires_)
 				if (match_ids(it.first, arg_memb.substr(2)))
 					sel.selected_members[mod->name].insert(it.first);
 		} else
 		if (arg_memb.substr(0, 2) == "i:") {
-			for (auto &it : mod->wires)
+			for (auto &it : mod->wires_)
 				if (it.second->port_input && match_ids(it.first, arg_memb.substr(2)))
 					sel.selected_members[mod->name].insert(it.first);
 		} else
 		if (arg_memb.substr(0, 2) == "o:") {
-			for (auto &it : mod->wires)
+			for (auto &it : mod->wires_)
 				if (it.second->port_output && match_ids(it.first, arg_memb.substr(2)))
 					sel.selected_members[mod->name].insert(it.first);
 		} else
 		if (arg_memb.substr(0, 2) == "x:") {
-			for (auto &it : mod->wires)
+			for (auto &it : mod->wires_)
 				if ((it.second->port_input || it.second->port_output) && match_ids(it.first, arg_memb.substr(2)))
 					sel.selected_members[mod->name].insert(it.first);
 		} else
@@ -723,7 +723,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
 			size_t delim = arg_memb.substr(2).find(':');
 			if (delim == std::string::npos) {
 				int width = atoi(arg_memb.substr(2).c_str());
-				for (auto &it : mod->wires)
+				for (auto &it : mod->wires_)
 					if (it.second->width == width)
 						sel.selected_members[mod->name].insert(it.first);
 			} else {
@@ -731,7 +731,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
 				std::string max_str = arg_memb.substr(2+delim+1);
 				int min_width = min_str.empty() ? 0 : atoi(min_str.c_str());
 				int max_width = max_str.empty() ? -1 : atoi(max_str.c_str());
-				for (auto &it : mod->wires)
+				for (auto &it : mod->wires_)
 					if (min_width <= it.second->width && (it.second->width <= max_width || max_width == -1))
 						sel.selected_members[mod->name].insert(it.first);
 			}
@@ -757,7 +757,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
 					sel.selected_members[mod->name].insert(it.first);
 		} else
 		if (arg_memb.substr(0, 2) == "a:") {
-			for (auto &it : mod->wires)
+			for (auto &it : mod->wires_)
 				if (match_attr(it.second->attributes, arg_memb.substr(2)))
 					sel.selected_members[mod->name].insert(it.first);
 			for (auto &it : mod->memories)
@@ -777,7 +777,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg)
 		} else {
 			if (arg_memb.substr(0, 2) == "n:")
 				arg_memb = arg_memb.substr(2);
-			for (auto &it : mod->wires)
+			for (auto &it : mod->wires_)
 				if (match_ids(it.first, arg_memb))
 					sel.selected_members[mod->name].insert(it.first);
 			for (auto &it : mod->memories)
@@ -1152,7 +1152,7 @@ struct SelectPass : public Pass {
 				if (sel->selected_whole_module(mod_it.first) && list_mode)
 					log("%s\n", id2cstr(mod_it.first));
 				if (sel->selected_module(mod_it.first)) {
-					for (auto &it : mod_it.second->wires)
+					for (auto &it : mod_it.second->wires_)
 						if (sel->selected_member(mod_it.first, it.first))
 							LOG_OBJECT("%s/%s\n", id2cstr(mod_it.first), id2cstr(it.first));
 					for (auto &it : mod_it.second->memories)
@@ -1219,7 +1219,7 @@ struct SelectPass : public Pass {
 			sel->optimize(design);
 			for (auto mod_it : design->modules)
 				if (sel->selected_module(mod_it.first)) {
-					for (auto &it : mod_it.second->wires)
+					for (auto &it : mod_it.second->wires_)
 						if (sel->selected_member(mod_it.first, it.first))
 							total_count++;
 					for (auto &it : mod_it.second->memories)
@@ -1374,7 +1374,7 @@ struct LsPass : public Pass {
 		if (design->modules.count(design->selected_active_module) > 0)
 		{
 			RTLIL::Module *module = design->modules.at(design->selected_active_module);
-			counter += log_matches("wires", pattern, module->wires);
+			counter += log_matches("wires", pattern, module->wires_);
 			counter += log_matches("memories", pattern, module->memories);
 			counter += log_matches("cells", pattern, module->cells);
 			counter += log_matches("processes", pattern, module->processes);

passes/cmds/setattr.cc

@@ -111,7 +111,7 @@ struct SetattrPass : public Pass {
 			if (!design->selected(module))
 				continue;
 
-			for (auto &it : module->wires)
+			for (auto &it : module->wires_)
 				if (design->selected(module, it.second))
 					do_setunset(it.second->attributes, setunset_list);
 

passes/cmds/setundef.cc

@@ -129,7 +129,7 @@ struct SetundefPass : public Pass {
 				SigMap sigmap(module);
 				SigPool undriven_signals;
 
-				for (auto &it : module->wires)
+				for (auto &it : module->wires_)
 					if (!it.second->port_input)
 						undriven_signals.add(sigmap(it.second));
 

passes/cmds/show.cc

@@ -305,7 +305,7 @@ struct ShowWorker
 		std::set<std::string> all_sources, all_sinks;
 
 		std::map<std::string, std::string> wires_on_demand;
-		for (auto &it : module->wires) {
+		for (auto &it : module->wires_) {
 			if (!design->selected_member(module->name, it.first))
 				continue;
 			const char *shape = "diamond";

passes/cmds/splice.cc

@@ -149,7 +149,7 @@ struct SpliceWorker
 		driven_bits.push_back(RTLIL::State::Sm);
 		driven_bits.push_back(RTLIL::State::Sm);
 
-		for (auto &it : module->wires)
+		for (auto &it : module->wires_)
 			if (it.second->port_input) {
 				RTLIL::SigSpec sig = sigmap(it.second);
 				driven_chunks.insert(sig);
@@ -175,7 +175,7 @@ struct SpliceWorker
 
 		SigPool selected_bits;
 		if (!sel_by_cell)
-			for (auto &it : module->wires)
+			for (auto &it : module->wires_)
 				if (design->selected(module, it.second))
 					selected_bits.add(sigmap(it.second));
 
@@ -203,7 +203,7 @@ struct SpliceWorker
 
 		std::vector<std::pair<RTLIL::Wire*, RTLIL::SigSpec>> rework_wires;
 
-		for (auto &it : module->wires)
+		for (auto &it : module->wires_)
 			if (!no_outputs && it.second->port_output) {
 				if (!design->selected(module, it.second))
 					continue;

passes/cmds/splitnets.cc

@@ -163,7 +163,7 @@ struct SplitnetsPass : public Pass {
 			}
 			else
 			{
-				for (auto &w : module->wires) {
+				for (auto &w : module->wires_) {
 					RTLIL::Wire *wire = w.second;
 					if (wire->width > 1 && (wire->port_id == 0 || flag_ports) && design->selected(module, w.second))
 						worker.splitmap[wire] = std::vector<RTLIL::SigBit>();

passes/cmds/stat.cc

@@ -69,7 +69,7 @@ namespace
 			STAT_INT_MEMBERS
 		#undef X
 
-			for (auto &it : mod->wires)
+			for (auto &it : mod->wires_)
 			{
 				if (!design->selected(mod, it.second))
 					continue;