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Refactoring: Renamed RTLIL::Module::wires to wires_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
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6
manual/PRESENTATION_Prog/my_cmd.cc
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@ -14,7 +14,7 @@ struct MyPass : public Pass {
log("Modules in current design:\n");
for (auto &mod : design->modules)
log(" %s (%zd wires, %zd cells)\n", RTLIL::id2cstr(mod.first),
mod.second->wires.size(), mod.second->cells.size());
mod.second->wires_.size(), mod.second->cells.size());
}
} MyPass;
@ -58,8 +58,8 @@ struct Test2Pass : public Pass {
RTLIL::Module *module = design->modules.at("\\test");
RTLIL::SigSpec a(module->wires.at("\\a")), x(module->wires.at("\\x")),
y(module->wires.at("\\y"));
RTLIL::SigSpec a(module->wires_.at("\\a")), x(module->wires_.at("\\x")),
y(module->wires_.at("\\y"));
log("%d %d %d\n", a == x, x == y, y == a); // will print "0 0 0"
SigMap sigmap(module);