mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-05 05:41:24 +00:00
Code Activity

Refactoring: Renamed RTLIL::Module::wires to wires_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
Download patch file Download diff file Expand all files Collapse all files

2
kernel/modwalker.h
View file

@ -121,7 +121,7 @@ struct ModWalker
signal_inputs.clear();
signal_outputs.clear();
for (auto &it : module->wires)
for (auto &it : module->wires_)
add_wire(it.second);
for (auto &it : module->cells)
if (filter_ct == NULL || filter_ct->cell_known(it.second->type))