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Refactoring: Renamed RTLIL::Module::wires to wires_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
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8
kernel/celltypes.h
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@ -181,8 +181,8 @@ struct CellTypes
if (cell_types.count(type) == 0) {
for (auto design : designs)
if (design->modules.count(type) > 0) {
if (design->modules.at(type)->wires.count(port))
return design->modules.at(type)->wires.at(port)->port_output;
if (design->modules.at(type)->wires_.count(port))
return design->modules.at(type)->wires_.at(port)->port_output;
return false;
}
return false;
@ -204,8 +204,8 @@ struct CellTypes
if (cell_types.count(type) == 0) {
for (auto design : designs)
if (design->modules.count(type) > 0) {
if (design->modules.at(type)->wires.count(port))
return design->modules.at(type)->wires.at(port)->port_input;
if (design->modules.at(type)->wires_.count(port))
return design->modules.at(type)->wires_.at(port)->port_input;
return false;
}
return false;