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Refactoring: Renamed RTLIL::Module::wires to wires_

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This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
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4
backends/spice/spice.cc
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@ -68,7 +68,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
RTLIL::Module *mod = design->modules.at(cell->type);
std::vector<RTLIL::Wire*> ports;
for (auto wire_it : mod->wires) {
for (auto wire_it : mod->wires_) {
RTLIL::Wire *wire = wire_it.second;
if (wire->port_id == 0)
continue;
@ -195,7 +195,7 @@ struct SpiceBackend : public Backend {
}
std::vector<RTLIL::Wire*> ports;
for (auto wire_it : module->wires) {
for (auto wire_it : module->wires_) {
RTLIL::Wire *wire = wire_it.second;
if (wire->port_id == 0)
continue;