mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-06-12 09:03:27 +00:00
Code Activity

Refactoring: Renamed RTLIL::Module::wires to wires_

Browse source
This commit is contained in:
Clifford Wolf 2014-07-27 01:49:51 +02:00
parent d7916a49af
commit f9946232ad
50 changed files with 191 additions and 191 deletions
Download patch file Download diff file Expand all files Collapse all files

2
backends/ilang/ilang_backend.cc
View file

@ -280,7 +280,7 @@ void ILANG_BACKEND::dump_module(FILE *f, std::string indent, const RTLIL::Module
if (print_body)
{
for (auto it = module->wires.begin(); it != module->wires.end(); it++)
for (auto it = module->wires_.begin(); it != module->wires_.end(); it++)
if (!only_selected || design->selected(module, it->second)) {
if (only_selected)
fprintf(f, "\n");