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This commit is contained in:
Eddie Hung 2019-08-22 12:35:35 -07:00
parent 9224b3bc17
commit f9906eed68
8 changed files with 11 additions and 10 deletions
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6
tests/ice40/mux.ys
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@ -1,8 +1,8 @@
read_verilog mux.v
proc
flatten
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40
design -load postopt
cd top
equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module
select -assert-count 19 t:SB_LUT4
select -assert-none t:SB_LUT4 %% t:* %D