mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-04-06 17:44:09 +00:00
Code Activity

Fix new tests

Browse source
This commit is contained in:
Miodrag Milanovic 2019-12-28 16:43:19 +01:00
parent 8c3de1d4bd
commit f9749c202c
3 changed files with 6 additions and 6 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
tests/arch/xilinx/dsp_cascade.ys
View file

@ -19,7 +19,7 @@ EOT
proc proc
design -save read design -save read
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad
design -load postopt design -load postopt
cd cascade cd cascade
select -assert-count 3 t:DSP48E1 select -assert-count 3 t:DSP48E1
@ -35,7 +35,7 @@ select -assert-none t:DSP48E1 t:BUFG %% t:* %D
select -assert-count 2 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i select -assert-count 2 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i
design -load read design -load read
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad
design -load postopt design -load postopt
cd cascade cd cascade
select -assert-count 3 t:DSP48A1 select -assert-count 3 t:DSP48A1
@ -65,7 +65,7 @@ EOT
proc proc
design -save read design -save read
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -noiopad
design -load postopt design -load postopt
cd cascade cd cascade
select -assert-count 2 t:DSP48E1 select -assert-count 2 t:DSP48E1
@ -75,7 +75,7 @@ select -assert-none t:DSP48E1 t:BUFG %% t:* %D
select -assert-count 1 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i select -assert-count 1 t:DSP48E1 %co:+[PCOUT] t:DSP48E1 %d %co:+[PCIN] w:* %d t:DSP48E1 %i
design -load read design -load read
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad
design -load postopt design -load postopt
cd cascade cd cascade
select -assert-count 2 t:DSP48A1 select -assert-count 2 t:DSP48A1

2
tests/arch/xilinx/mul.ys
View file

@ -13,7 +13,7 @@ design -reset
read_verilog ../common/mul.v read_verilog ../common/mul.v
hierarchy -top top hierarchy -top top
proc proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s # equivalency check equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd top # Constrain all select calls below inside the top module cd top # Constrain all select calls below inside the top module

2
tests/arch/xilinx/mul_unsigned.ys
View file

@ -16,7 +16,7 @@ read_verilog mul_unsigned.v
hierarchy -top mul_unsigned hierarchy -top mul_unsigned
proc proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s # equivalency check equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mul_unsigned # Constrain all select calls below inside the top module cd mul_unsigned # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG select -assert-count 1 t:BUFG