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Fix new tests

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This commit is contained in:
Miodrag Milanovic 2019-12-28 16:43:19 +01:00
parent 8c3de1d4bd
commit f9749c202c
3 changed files with 6 additions and 6 deletions
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2
tests/arch/xilinx/mul_unsigned.ys
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@ -16,7 +16,7 @@ read_verilog mul_unsigned.v
hierarchy -top mul_unsigned
proc
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s # equivalency check
equiv_opt -assert -map +/xilinx/cells_sim.v synth_xilinx -family xc6s -noiopad # equivalency check
design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
cd mul_unsigned # Constrain all select calls below inside the top module
select -assert-count 1 t:BUFG