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rtlil: Disallow 0-width chunks in SigSpec.

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Among other problems, this also fixes equality comparisons between
SigSpec by enforcing a canonical form.

Also fix another minor issue with possible non-canonical SigSpec.

Fixes #2623.
This commit is contained in:
Marcelina Kościelnicka 2021-03-09 02:54:56 +01:00
parent e178d0367a
commit f965b3fa54
2 changed files with 63 additions and 18 deletions
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14
tests/opt/bug2623.ys Normal file
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@ -0,0 +1,14 @@
read_rtlil << EOT
module \top
wire output 1 \a
wire width 0 $dummy
cell \abc \abc
connect \a \a
connect \b $dummy
end
end
EOT
opt_clean