mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-12-11 14:16:24 +00:00
Code Activity

GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow

Browse source
This commit is contained in:
Diego 2019-04-12 23:40:02 -05:00
parent db1a5ec6a2
commit f9272fc56d
10 changed files with 459 additions and 11 deletions
Download patch file Download diff file Expand all files Collapse all files

17
techlibs/gowin/dram.txt Normal file
View file

@ -0,0 +1,17 @@
bram $__GW1NR_RAM16S4
init 1
abits 4
dbits 4
groups 2
ports 1 1
wrmode 0 1
enable 0 1
transp 0 1
clocks 0 1
clkpol 0 1
endbram
match $__GW1NR_RAM16S4
make_outreg
min wports 1
endmatch