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Eddie Hung 2019-10-05 08:57:37 -07:00
parent 991c2ca95b
commit f90a4b1e24
1 changed files with 4 additions and 3 deletions
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7
passes/pmgen/xilinx_dsp_CREG.pmg
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@ -105,9 +105,10 @@ endcode
// #######################
// Subpattern for matching against input registers, based on knowledge of the
// 'Q' input. Typically, this task would be handled by other Yosys passes
// such as dff2dffe, but since DSP inference happens much before this, these
// patterns have to be manually identified.
// 'Q' input. Typically, identifying registers with clock-enable and reset
// capability would be a task would be handled by other Yosys passes such as
// dff2dffe, but since DSP inference happens much before this, these patterns
// have to be manually identified.
// At a high level:
// (1) Starting from a $dff cell that (partially or fully) drives the given
// 'Q' argument