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Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"

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David Shah 2019-08-10 17:14:48 +01:00 • committed by GitHub
parent f54bf1631f
commit f9020ce2b3
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20 changed files with 181 additions and 181 deletions
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33
tests/various/wreduce.ys
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@ -36,6 +36,7 @@ design -save gold
opt_expr
wreduce
dump
select -assert-count 1 t:$sub r:A_WIDTH=4 r:B_WIDTH=4 r:Y_WIDTH=5 %i %i %i
design -stash gate
@ -45,35 +46,3 @@ design -import gate -as gate
miter -equiv -flatten -make_assert -make_outputs gold gate miter
sat -verify -prove-asserts -show-ports miter
##########
# Testcase from: https://github.com/YosysHQ/yosys/commit/25680f6a078bb32f157bd580705656496717bafb
design -reset
read_verilog <<EOT
module top(
input clk,
input rst,
input [2:0] a,
output [1:0] b
);
reg [2:0] b_reg;
initial begin
b_reg <= 3'b0;
end
assign b = b_reg[1:0];
always @(posedge clk or posedge rst) begin
if(rst) begin
b_reg <= 3'b0;
end else begin
b_reg <= a;
end
end
endmodule
EOT
proc
wreduce
select -assert-count 1 t:$adff r:ARST_VALUE=2'b00 %i