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Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"

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David Shah 2019-08-10 17:14:48 +01:00 • committed by GitHub
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commit f9020ce2b3
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20 changed files with 181 additions and 181 deletions
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tests/opt/opt_lut.ys
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@ -1,2 +1,4 @@
read_verilog opt_lut.v
equiv_opt -map +/ice40/cells_sim.v -assert synth_ice40
synth_ice40
ice40_unlut
equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3