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Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"

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David Shah 2019-08-10 17:14:48 +01:00 • committed by GitHub
parent f54bf1631f
commit f9020ce2b3
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20 changed files with 181 additions and 181 deletions
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9
techlibs/ice40/tests/test_arith.ys
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@ -1,5 +1,6 @@
read_verilog test_arith.v
synth_ice40
techmap -map ../cells_sim.v
rename test gate
read_verilog test_arith.v
@ -7,11 +8,3 @@ rename test gold
miter -equiv -flatten -make_outputs gold gate miter
sat -verify -prove trigger 0 -show-ports miter
synth_ice40 -top gate
read_verilog test_arith.v
rename test gold
miter -equiv -flatten -make_outputs gold gate miter
sat -verify -prove trigger 0 -show-ports miter