mirrors/yosys
3
0
Fork 0
mirror of https://github.com/YosysHQ/yosys synced 2025-07-24 05:08:56 +00:00
Code Activity

Manual fixes for new cell connections API

Browse source
This commit is contained in:
Clifford Wolf 2014-07-26 15:57:57 +02:00
parent b7dda72302
commit f8fdc47d33
36 changed files with 169 additions and 123 deletions
Download patch file Download diff file Expand all files Collapse all files

8
passes/techmap/iopadmap.cc
View file

@ -177,9 +177,9 @@ struct IopadmapPass : public Pass {
for (int i = 0; i < wire->width; i++)
{
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
cell->connections()[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire, i);
cell->set(RTLIL::escape_id(portname), RTLIL::SigSpec(wire, i));
if (!portname2.empty())
cell->connections()[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire, i);
cell->set(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire, i));
if (!widthparam.empty())
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(1);
if (!nameparam.empty())
@ -190,9 +190,9 @@ struct IopadmapPass : public Pass {
else
{
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(celltype));
cell->connections()[RTLIL::escape_id(portname)] = RTLIL::SigSpec(wire);
cell->set(RTLIL::escape_id(portname), RTLIL::SigSpec(wire));
if (!portname2.empty())
cell->connections()[RTLIL::escape_id(portname2)] = RTLIL::SigSpec(new_wire);
cell->set(RTLIL::escape_id(portname2), RTLIL::SigSpec(new_wire));
if (!widthparam.empty())
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
if (!nameparam.empty())