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Manual fixes for new cell connections API

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This commit is contained in:
Clifford Wolf 2014-07-26 15:57:57 +02:00
parent b7dda72302
commit f8fdc47d33
36 changed files with 169 additions and 123 deletions
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4
passes/techmap/hilomap.cc
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@ -35,7 +35,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
if (!singleton_mode || last_hi == RTLIL::State::Sm) {
last_hi = module->addWire(NEW_ID);
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(hicell_celltype));
cell->connections()[RTLIL::escape_id(hicell_portname)] = last_hi;
cell->set(RTLIL::escape_id(hicell_portname), last_hi);
}
bit = last_hi;
}
@ -43,7 +43,7 @@ void hilomap_worker(RTLIL::SigSpec &sig)
if (!singleton_mode || last_lo == RTLIL::State::Sm) {
last_lo = module->addWire(NEW_ID);
RTLIL::Cell *cell = module->addCell(NEW_ID, RTLIL::escape_id(locell_celltype));
cell->connections()[RTLIL::escape_id(locell_portname)] = last_lo;
cell->set(RTLIL::escape_id(locell_portname), last_lo);
}
bit = last_lo;
}