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Manual fixes for new cell connections API

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This commit is contained in:
Clifford Wolf 2014-07-26 15:57:57 +02:00
parent b7dda72302
commit f8fdc47d33
36 changed files with 169 additions and 123 deletions
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2
passes/cmds/add.cc
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@ -78,7 +78,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n
if (it.second->connections().count(name) > 0)
continue;
it.second->connections()[name] = wire;
it.second->set(name, wire);
log("Added connection %s to cell %s.%s (%s).\n", name.c_str(), module->name.c_str(), it.first.c_str(), it.second->type.c_str());
}
}

6
passes/cmds/connect.cc
View file

@ -30,11 +30,11 @@ static void unset_drivers(RTLIL::Design *design, RTLIL::Module *module, SigMap &
RTLIL::Wire *dummy_wire = module->addWire(NEW_ID, sig.size());
for (auto &it : module->cells)
for (auto &port : it.second->connections())
for (auto &port : it.second->connections_)
if (ct.cell_output(it.second->type, port.first))
sigmap(port.second).replace(sig, dummy_wire, &port.second);
for (auto &conn : module->connections())
for (auto &conn : module->connections_)
sigmap(conn.first).replace(sig, dummy_wire, &conn.first);
}
@ -176,7 +176,7 @@ struct ConnectPass : public Pass {
if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr))
log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str());
module->cells.at(RTLIL::escape_id(port_cell))->connections()[RTLIL::escape_id(port_port)] = sigmap(sig);
module->cells.at(RTLIL::escape_id(port_cell))->set(RTLIL::escape_id(port_port), sigmap(sig));
}
else
log_cmd_error("Expected -set, -unset, or -port.\n");

2
passes/cmds/connwrappers.cc
View file

@ -109,7 +109,7 @@ struct ConnwrappersWorker
if (!design->selected(module, cell))
continue;
for (auto &conn : cell->connections())
for (auto &conn : cell->connections_)
{
std::vector<RTLIL::SigBit> sigbits = sigmap(conn.second).to_sigbit_vector();
RTLIL::SigSpec old_sig;

2
passes/cmds/scatter.cc
View file

@ -49,7 +49,7 @@ struct ScatterPass : public Pass {
continue;
for (auto &c : mod_it.second->cells)
for (auto &p : c.second->connections())
for (auto &p : c.second->connections_)
{
RTLIL::Wire *wire = new RTLIL::Wire;
wire->name = NEW_ID;

6
passes/cmds/show.cc
View file

@ -87,17 +87,17 @@ struct ShowWorker
return defaultColor;
}
std::string nextColor(RTLIL::SigSig &conn, std::string defaultColor)
std::string nextColor(const RTLIL::SigSig &conn, std::string defaultColor)
{
return nextColor(conn.first, nextColor(conn.second, defaultColor));
}
std::string nextColor(RTLIL::SigSpec &sig)
std::string nextColor(const RTLIL::SigSpec &sig)
{
return nextColor(sig, nextColor());
}
std::string nextColor(RTLIL::SigSig &conn)
std::string nextColor(const RTLIL::SigSig &conn)
{
return nextColor(conn, nextColor());
}

2
passes/cmds/splice.cc
View file

@ -182,7 +182,7 @@ struct SpliceWorker
for (auto &it : module->cells) {
if (!sel_by_wire && !design->selected(module, it.second))
continue;
for (auto &conn : it.second->connections())
for (auto &conn : it.second->connections_)
if (ct.cell_input(it.second->type, conn.first)) {
if (ports.size() > 0 && !ports.count(conn.first))
continue;