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Manual fixes for new cell connections API
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36 changed files with 169 additions and 123 deletions
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@ -785,7 +785,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
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assert(c.width == 1);
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newsig.append(module->wires[remap_name(c.wire->name)]);
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}
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cell->connections()[conn.first] = newsig;
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cell->set(conn.first, newsig);
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}
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design->select(module, cell);
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}
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