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Manual fixes for new cell connections API

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This commit is contained in:
Clifford Wolf 2014-07-26 15:57:57 +02:00
parent b7dda72302
commit f8fdc47d33
36 changed files with 169 additions and 123 deletions
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2
passes/abc/abc.cc
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@ -785,7 +785,7 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
assert(c.width == 1);
newsig.append(module->wires[remap_name(c.wire->name)]);
}
cell->connections()[conn.first] = newsig;
cell->set(conn.first, newsig);
}
design->select(module, cell);
}

2
passes/abc/blifparse.cc
View file

@ -148,7 +148,7 @@ RTLIL::Design *abc_parse_blif(FILE *f, std::string dff_name)
*(q++) = 0;
if (module->wires.count(RTLIL::escape_id(q)) == 0)
module->addWire(RTLIL::escape_id(q));
cell->connections()[RTLIL::escape_id(p)] = module->wires.at(RTLIL::escape_id(q));
cell->set(RTLIL::escape_id(p), module->wires.at(RTLIL::escape_id(q)));
}
continue;
}