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Use ripple as default final adder, gate fma.

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nella 2026-06-03 15:13:20 +02:00
parent 11a650c695
commit f8d2252735
4 changed files with 29 additions and 31 deletions
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6
tests/arith_tree/arith_tree_defaults.ys
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@ -52,9 +52,9 @@ proc
equiv_opt arith_tree
design -load postopt
select -assert-count 2 t:$fa
select -assert-none t:$add
select -assert-min 1 t:$_AND_
select -assert-min 1 t:$_XOR_
select -assert-count 1 t:$add
select -assert-min 0 t:$_AND_
select -assert-min 0 t:$_XOR_
design -reset
read_verilog <<EOT