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	Move lookup inside if
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					 1 changed files with 2 additions and 2 deletions
				
			
		|  | @ -455,9 +455,9 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri | ||||||
| 			RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w)); | 			RTLIL::Wire *remap_wire = module->addWire(remap_name(w->name), GetSize(w)); | ||||||
| 			if (markgroups) remap_wire->attributes["\\abcgroup"] = map_autoidx; | 			if (markgroups) remap_wire->attributes["\\abcgroup"] = map_autoidx; | ||||||
| 			design->select(module, remap_wire); | 			design->select(module, remap_wire); | ||||||
| 			RTLIL::Wire *wire = module->wire(w->name); |  | ||||||
| 			if (w->port_output) { | 			if (w->port_output) { | ||||||
| 				for (int i = 0; i < GetSize(remap_wire); i++) | 				RTLIL::Wire *wire = module->wire(w->name); | ||||||
|  | 				for (int i = 0; i < GetSize(wire); i++) | ||||||
| 					output_bits.insert({wire, i}); | 					output_bits.insert({wire, i}); | ||||||
| 			} | 			} | ||||||
| 		} | 		} | ||||||
|  |  | ||||||
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