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add wide luts

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This commit is contained in:
Pepijn de Vos 2019-10-28 12:49:08 +01:00
parent 5fad53b504
commit f88335a8a5
3 changed files with 119 additions and 36 deletions
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24
techlibs/gowin/cells_map.v
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@ -101,6 +101,30 @@ module \$lut (A, Y);
if (WIDTH == 4) begin
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.F(Y),
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
end else
if (WIDTH == 5) begin
wire f0, f1;
\$lut #(.LUT(LUT[15: 0]), .WIDTH(4)) lut0 (.A(A[1:4]), .Y(f0));
\$lut #(.LUT(LUT[31:16]), .WIDTH(4)) lut1 (.A(A[1:4]), .Y(f1));
MUX2_LUT5 mux5(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
end else
if (WIDTH == 6) begin
wire f0, f1;
\$lut #(.LUT(LUT[31: 0]), .WIDTH(5)) lut0 (.A(A[1:5]), .Y(f0));
\$lut #(.LUT(LUT[63:32]), .WIDTH(5)) lut1 (.A(A[1:5]), .Y(f1));
MUX2_LUT6 mux6(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
end else
if (WIDTH == 7) begin
wire f0, f1;
\$lut #(.LUT(LUT[63: 0]), .WIDTH(6)) lut0 (.A(A[1:6]), .Y(f0));
\$lut #(.LUT(LUT[127:64]), .WIDTH(6)) lut1 (.A(A[1:6]), .Y(f1));
MUX2_LUT7 mux7(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
end else
if (WIDTH == 8) begin
wire f0, f1;
\$lut #(.LUT(LUT[127: 0]), .WIDTH(7)) lut0 (.A(A[1:7]), .Y(f0));
\$lut #(.LUT(LUT[255:128]), .WIDTH(7)) lut1 (.A(A[1:7]), .Y(f1));
MUX2_LUT8 mux8(.I0(f0), .I1(f1), .S0(A[0]), .O(Y));
end else begin
wire _TECHMAP_FAIL_ = 1;
end