read_verilog: add -relativeshare for synthesis reproducibility testing

frontends/verilog/verilog_frontend.cc

@@ -229,6 +229,10 @@ struct VerilogFrontend : public Frontend {
 		log("        add 'dir' to the directories which are used when searching include\n");
 		log("        files\n");
 		log("\n");
+		log("    -relativeshare\n");
+		log("        use paths relative to share directory for source locations\n");
+		log("        where possible (experimental).\n");
+		log("\n");
 		log("The command 'verilog_defaults' can be used to register default options for\n");
 		log("subsequent calls to 'read_verilog'.\n");
 		log("\n");
@@ -273,6 +277,7 @@ struct VerilogFrontend : public Frontend {
 		bool flag_nowb = false;
 		bool flag_nosynthesis = false;
 		bool flag_yydebug = false;
+		bool flag_relative_share = false;
 		define_map_t defines_map;
 
 		std::list<std::string> include_dirs;
@@ -450,6 +455,11 @@ struct VerilogFrontend : public Frontend {
 				attributes.push_back(RTLIL::escape_id(args[++argidx]));
 				continue;
 			}
+			if (arg == "-relativeshare") {
+				flag_relative_share = true;
+				log_experimental("read_verilog -relativeshare");
+				continue;
+			}
 			if (arg == "-D" && argidx+1 < args.size()) {
 				std::string name = args[++argidx], value;
 				size_t equal = name.find('=');
@@ -490,6 +500,13 @@ struct VerilogFrontend : public Frontend {
 		log("Parsing %s%s input from `%s' to AST representation.\n",
 				parse_mode.formal ? "formal " : "", parse_mode.sv ? "SystemVerilog" : "Verilog", filename.c_str());
 
+		log("verilog frontend filename %s\n", filename.c_str());
+		if (flag_relative_share) {
+			auto share_path = proc_share_dirname();
+			if (filename.substr(0, share_path.length()) == share_path)
+				filename = std::string("+/") + filename.substr(share_path.length());
+			log("new filename %s\n", filename.c_str());
+		}
 		AST::sv_mode_but_global_and_used_for_literally_one_condition = parse_mode.sv;
 		std::string code_after_preproc;
 

passes/techmap/techmap.cc

@@ -1031,6 +1031,10 @@ struct TechmapPass : public Pass {
 		log("    -dont_map <celltype>\n");
 		log("        leave the given cell type unmapped by ignoring any mapping rules for it\n");
 		log("\n");
+		log("    -relativeshare\n");
+		log("        use paths relative to share directory for source locations\n");
+		log("        where possible (experimental).\n");
+		log("\n");
 		log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
 		log("match cells with a type that match the text value of this attribute. Otherwise\n");
 		log("the module name will be used to match the cell.  Multiple space-separated cell\n");
@@ -1184,6 +1188,11 @@ struct TechmapPass : public Pass {
 				verilog_frontend += " -I " + args[++argidx];
 				continue;
 			}
+			if (args[argidx] == "-relativeshare") {
+				verilog_frontend += " -relativeshare";
+				log_experimental("techmap -relativeshare");
+				continue;
+			}
 			if (args[argidx] == "-assert") {
 				worker.assert_mode = true;
 				continue;

techlibs/common/synth.cc

@@ -98,13 +98,17 @@ struct SynthPass : public ScriptPass {
 		log("        mapping library in the `techmap` step. this option can be\n");
 		log("        repeated.\n");
 		log("\n");
+		log("    -relativeshare\n");
+		log("        use paths relative to share directory for source locations\n");
+		log("        where possible (experimental).\n");
+		log("\n");
 		log("The following commands are executed by this synthesis command:\n");
 		help_script();
 		log("\n");
 	}
 
 	string top_module, fsm_opts, memory_opts, abc;
-	bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, hieropt;
+	bool autotop, flatten, noalumacc, nofsm, noabc, noshare, flowmap, booth, hieropt, relative_share;
 	int lut;
 	std::vector<std::string> techmap_maps;
 
@@ -124,6 +128,7 @@ struct SynthPass : public ScriptPass {
 		flowmap = false;
 		booth = false;
 		hieropt = false;
+		relative_share = false;
 		abc = "abc";
 		techmap_maps.clear();
 	}
@@ -211,6 +216,11 @@ struct SynthPass : public ScriptPass {
 				hieropt = true;
 				continue;
 			}
+			if (args[argidx] == "-relativeshare") {
+				relative_share = true;
+				log_experimental("synth -relativeshare");
+				continue;
+			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -239,6 +249,10 @@ struct SynthPass : public ScriptPass {
 		else
 			hieropt_flag = hieropt ? " -hier" : "";
 
+		std::string techmap_cmd = "techmap";
+		if (relative_share)
+			techmap_cmd += " -relativeshare";
+
 		if (check_label("begin")) {
 			if (help_mode) {
 				run("hierarchy -check [-top <top> | -auto-top]");
@@ -268,9 +282,9 @@ struct SynthPass : public ScriptPass {
 			run("peepopt");
 			run("opt_clean");
 			if (help_mode)
-				run("techmap -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)");
+				run(techmap_cmd + " -map +/cmp2lut.v -map +/cmp2lcu.v", " (if -lut)");
 			else if (lut)
-				run(stringf("techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", lut));
+				run(stringf("%s -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=%d", techmap_cmd, lut));
 			if (booth || help_mode)
 				run("booth", "    (if -booth)");
 			if (!noalumacc)
@@ -287,22 +301,22 @@ struct SynthPass : public ScriptPass {
 			run("memory_map");
 			run("opt -full");
 			if (help_mode) {
-				run("techmap", "                  (unless -extra-map)");	
+				run(techmap_cmd, "                  (unless -extra-map)");	
-				run("techmap -map +/techmap.v -map <inject>", "  (if -extra-map)");
+				run(techmap_cmd + " -map +/techmap.v -map <inject>", "  (if -extra-map)");
 			} else {
 				std::string techmap_opts;
 				if (!techmap_maps.empty())
 					techmap_opts += " -map +/techmap.v";
 				for (auto fn : techmap_maps)
 					techmap_opts += stringf(" -map %s", fn.c_str());
-				run("techmap" + techmap_opts);
+				run(techmap_cmd + techmap_opts);
 			}
 			if (help_mode) {
-				run("techmap -map +/gate2lut.v", "(if -noabc and -lut)");
+				run(techmap_cmd + " -map +/gate2lut.v", "(if -noabc and -lut)");
 				run("clean; opt_lut", "           (if -noabc and -lut)");
 				run("flowmap -maxlut K", "        (if -flowmap and -lut)");
 			} else if (noabc && lut) {
-				run(stringf("techmap -map +/gate2lut.v -D LUT_WIDTH=%d", lut));
+				run(stringf("%s -map +/gate2lut.v -D LUT_WIDTH=%d", techmap_cmd, lut));
 				run("clean; opt_lut");
 			} else if (flowmap) {
 				run(stringf("flowmap -maxlut %d", lut));

techlibs/fabulous/synth_fabulous.cc

@@ -69,7 +69,7 @@ struct SynthPass : public ScriptPass
 		log("        use the specified Verilog file for extra primitives (can be specified multiple\n");
 		log("        times).\n");
 		log("\n");
-		log("    -extra-map <techamp.v>\n");
+		log("    -extra-map <techmap.v>\n");
 		log("        use the specified Verilog file for extra techmap rules (can be specified multiple\n");
 		log("        times).\n");
 		log("\n");

tests/functional/test_functional.py

@@ -24,7 +24,7 @@ def compile_cpp(in_path, out_path, args):
     run(['g++', '-g', '-std=c++17'] + args + [str(in_path), '-o', str(out_path)])
 
 def yosys_synth(verilog_file, rtlil_file):
-    yosys(f"read_verilog {quote(verilog_file)} ; prep ; setundef -undriven ; write_rtlil {quote(rtlil_file)}")
+    yosys(f"read_verilog {quote(verilog_file)} ; prep ; setundef -undriven -undef ; write_rtlil {quote(rtlil_file)}")
 
 # simulate an rtlil file with yosys, comparing with a given vcd file, and writing out the yosys simulation results into a second vcd file
 def yosys_sim(rtlil_file, vcd_reference_file, vcd_out_file, preprocessing = ""):
@@ -91,4 +91,4 @@ def test_print_graph(tmp_path):
     tb_file = base_path / 'tests/functional/picorv32_tb.v'
     cpu_file = base_path / 'tests/functional/picorv32.v'
     # currently we only check that we can print the graph without getting an error, not that it prints anything sensibl
-    yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; setundef -undriven ; flatten; clk2fflogic; test_generic")
+    yosys(f"read_verilog {quote(tb_file)} {quote(cpu_file)}; prep -top gold; setundef -undriven -undef ; flatten; clk2fflogic; test_generic")