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read_verilog: add -relativeshare for synthesis reproducibility testing

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Emil J. Tywoniak 2025-09-03 01:57:17 +02:00
parent 6c4d00ca7a
commit f8630d0777
5 changed files with 51 additions and 11 deletions
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2
techlibs/fabulous/synth_fabulous.cc
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@ -69,7 +69,7 @@ struct SynthPass : public ScriptPass
log(" use the specified Verilog file for extra primitives (can be specified multiple\n");
log(" times).\n");
log("\n");
log(" -extra-map <techamp.v>\n");
log(" -extra-map <techmap.v>\n");
log(" use the specified Verilog file for extra techmap rules (can be specified multiple\n");
log(" times).\n");
log("\n");