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read_verilog: add -relativeshare for synthesis reproducibility testing

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This commit is contained in:
Emil J. Tywoniak 2025-09-03 01:57:17 +02:00
parent 6c4d00ca7a
commit f8630d0777
5 changed files with 51 additions and 11 deletions
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9
passes/techmap/techmap.cc
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@ -1031,6 +1031,10 @@ struct TechmapPass : public Pass {
log(" -dont_map <celltype>\n");
log(" leave the given cell type unmapped by ignoring any mapping rules for it\n");
log("\n");
log(" -relativeshare\n");
log(" use paths relative to share directory for source locations\n");
log(" where possible (experimental).\n");
log("\n");
log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n");
log("match cells with a type that match the text value of this attribute. Otherwise\n");
log("the module name will be used to match the cell. Multiple space-separated cell\n");
@ -1184,6 +1188,11 @@ struct TechmapPass : public Pass {
verilog_frontend += " -I " + args[++argidx];
continue;
}
if (args[argidx] == "-relativeshare") {
verilog_frontend += " -relativeshare";
log_experimental("techmap -relativeshare");
continue;
}
if (args[argidx] == "-assert") {
worker.assert_mode = true;
continue;