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Cleanup tests

This commit is contained in:
Eddie Hung 2020-02-15 08:29:10 -08:00
parent 717fb492b3
commit f858219c4e
2 changed files with 1 additions and 1 deletions

View file

@ -1,18 +0,0 @@
read_verilog << EOF
module top(...);
input signed [17:0] A;
input signed [17:0] B;
output X;
output Y;
wire [35:0] P;
assign P = A * B;
assign X = P[0];
assign Y = P[35];
endmodule
EOF
synth_xilinx

View file

@ -33,7 +33,7 @@ module pmux2shiftx_test (
end
endmodule
module issue01135(input [7:0] i, output o);
module issue01135(input [7:0] i, output reg o);
always @*
case (i[6:3])
4: o <= i[0];