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Cleanup tests
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2 changed files with 1 additions and 1 deletions
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@ -1,18 +0,0 @@
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read_verilog << EOF
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module top(...);
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input signed [17:0] A;
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input signed [17:0] B;
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output X;
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output Y;
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wire [35:0] P;
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assign P = A * B;
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assign X = P[0];
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assign Y = P[35];
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endmodule
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EOF
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synth_xilinx
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@ -33,7 +33,7 @@ module pmux2shiftx_test (
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end
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endmodule
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module issue01135(input [7:0] i, output o);
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module issue01135(input [7:0] i, output reg o);
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always @*
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case (i[6:3])
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4: o <= i[0];
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