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Merge branch 'YosysHQ:main' into main

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This commit is contained in:
Akash Levy 2024-11-21 00:34:49 -08:00 • committed by GitHub
commit f855b39dbb
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16 changed files with 4870 additions and 128 deletions
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4
passes/opt/opt_demorgan.cc
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@ -39,6 +39,10 @@ void demorgan_worker(
return;
auto insig = sigmap(cell->getPort(ID::A));
if (GetSize(insig) < 1)
return;
log("Inspecting %s cell %s (%d inputs)\n", log_id(cell->type), log_id(cell->name), GetSize(insig));
int num_inverted = 0;
for(int i=0; i<GetSize(insig); i++)

3
passes/opt/opt_reduce.cc
View file

@ -89,6 +89,9 @@ struct OptReduceWorker
RTLIL::SigSpec new_sig_a(new_sig_a_bits);
new_sig_a.sort_and_unify();
if (GetSize(new_sig_a) == 0)
new_sig_a = (cell->type == ID($reduce_or)) ? State::S0 : State::S1;
if (new_sig_a != sig_a || sig_a.size() != cell->getPort(ID::A).size()) {
log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));
did_something = true;