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memory_share: Fix SAT-based sharing for wide ports.

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Fixes #3117.
This commit is contained in:
Marcelina Kościelnicka 2021-12-20 17:10:30 +01:00
parent f599c148c5
commit f84c9d8e17
2 changed files with 37 additions and 1 deletions
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4
passes/memory/memory_share.cc
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@ -416,7 +416,9 @@ struct MemoryShareWorker
else else
this_addr.extend_u0(GetSize(last_addr)); this_addr.extend_u0(GetSize(last_addr));
port1.addr = module->Mux(NEW_ID, last_addr, this_addr, this_en_active); SigSpec new_addr = module->Mux(NEW_ID, last_addr.extract_end(port1.wide_log2), this_addr.extract_end(port1.wide_log2), this_en_active);
port1.addr = SigSpec({new_addr, port1.addr.extract(0, port1.wide_log2)});
port1.data = module->Mux(NEW_ID, last_data, this_data, this_en_active); port1.data = module->Mux(NEW_ID, last_data, this_data, this_en_active);
std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en; std::map<std::pair<RTLIL::SigBit, RTLIL::SigBit>, int> groups_en;

34
tests/opt/bug3117.ys Normal file
View file

@ -0,0 +1,34 @@
read_verilog << EOT
module test (...);
input [7:1] wa1;
input [7:1] wa2;
input [7:0] ra;
output [7:0] rd;
input clk;
input we1, we2;
input [15:0] wd1, wd2;
reg [7:0] mem [0:255];
assign rd = mem[ra];
always @(posedge clk) begin
if (we1) begin
mem[{wa1, 1'b0}] <= wd1[7:0];
mem[{wa1, 1'b1}] <= wd1[15:8];
end else begin
mem[{wa2, 1'b0}] <= wd2[7:0];
mem[{wa2, 1'b1}] <= wd2[15:8];
end
end
endmodule
EOT
proc
opt
memory_share
select -assert-count 1 t:$memwr_v2