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Merge pull request #943 from YosysHQ/clifford/whitebox

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[WIP] Add "whitebox" attribute, add "read_verilog -wb"
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Clifford Wolf 2019-04-20 20:51:54 +02:00 • committed by GitHub
commit f84a84e3f1
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27 changed files with 157 additions and 55 deletions
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4
passes/cmds/show.cc
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@ -574,7 +574,7 @@ struct ShowWorker
if (!design->selected_module(module->name))
continue;
if (design->selected_whole_module(module->name)) {
if (module->get_bool_attribute("\\blackbox")) {
if (module->get_blackbox_attribute()) {
// log("Skipping blackbox module %s.\n", id2cstr(module->name));
continue;
} else
@ -790,7 +790,7 @@ struct ShowPass : public Pass {
if (format != "ps" && format != "dot") {
int modcount = 0;
for (auto &mod_it : design->modules_) {
if (mod_it.second->get_bool_attribute("\\blackbox"))
if (mod_it.second->get_blackbox_attribute())
continue;
if (mod_it.second->cells_.empty() && mod_it.second->connections().empty())
continue;