From f8325f66b7ae31111f2fe5b084bd8d96789c3747 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Martin=20Povi=C5=A1er?= Date: Tue, 1 Aug 2023 11:10:27 +0200 Subject: [PATCH] opt_expr: Fix 'signed X>=0' replacement for wide output ports If the `$ge` cell we are replacing has wide output port, the upper bits on the port should be driven to zero. That's not what a `$not` cell with a single-bit input does. Instead opt for a `$logic_not` cell, which does zero-pad its output. Fixes #3867. --- passes/opt/opt_expr.cc | 2 +- tests/opt/bug3867.ys | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) create mode 100644 tests/opt/bug3867.ys diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc index 9d5ca4ef9..46773a344 100644 --- a/passes/opt/opt_expr.cc +++ b/passes/opt/opt_expr.cc @@ -2165,7 +2165,7 @@ skip_alu_split: { condition = "signed X>=0"; replacement = stringf("X[%d]", var_width - 1); - module->addNot(NEW_ID, var_sig[var_width - 1], cell->getPort(ID::Y)); + module->addLogicNot(NEW_ID, var_sig[var_width - 1], cell->getPort(ID::Y)); remove = true; } } diff --git a/tests/opt/bug3867.ys b/tests/opt/bug3867.ys new file mode 100644 index 000000000..9c4359a78 --- /dev/null +++ b/tests/opt/bug3867.ys @@ -0,0 +1,7 @@ +read_verilog <= 0); +endmodule +EOF + +equiv_opt -assert opt_expr -fine