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Genericising bug1836.ys

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This commit is contained in:
KrystalDelusion 2022-07-25 10:21:00 +12:00
parent 445a801a85
commit f80920bd9f
1 changed files with 12 additions and 20 deletions
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32
tests/arch/ecp5/bug1836.ys
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@ -1,31 +1,23 @@
read_verilog <<EOT read_verilog <<EOT
module dds(input clk, output reg [15:0] signal1, output reg [15:0] signal2); module top(
reg [9:0] phase_accumulator_1; input clk,
reg [9:0] phase_accumulator_2; output reg [15:0] sig1, sig2
reg [15:0] sine_table [0:255]; );
reg [7:0] ptr1, ptr2;
reg [15:0] mem [0:255];
initial begin initial begin
$readmemh("bug1836.mem",sine_table); $readmemh("bug1836.mem", mem);
end end
always @(posedge clk) begin always @(posedge clk) begin
phase_accumulator_1 <= phase_accumulator_1 + 1; sig1 <= mem[ptr1];
phase_accumulator_2 <= phase_accumulator_2 + 2; ptr1 <= ptr1 + 3;
sig2 <= mem[ptr2];
ptr2 <= ptr2 + 7;
end end
always @(posedge clk) begin
signal1 <= sine_table[phase_accumulator_1[9:2]];
//signal2 <= sine_table[phase_accumulator_2[9:2]];
end
//comment out this always block below to test for single port read
always @(posedge clk) begin
//signal1 <= sine_table[phase_accumulator_1[9:2]];
signal2 <= sine_table[phase_accumulator_2[9:2]];
end
endmodule endmodule
EOT EOT
synth_ecp5 -top dds synth_ecp5 -top top
select -assert-count 1 t:DP16KD select -assert-count 1 t:DP16KD