From 8382980927440afaa04cfb40e6432b5f21c5fa00 Mon Sep 17 00:00:00 2001 From: Dhaval Chaudhari Date: Fri, 2 Jan 2026 18:21:42 +0530 Subject: [PATCH 1/4] verific: add support for setting VHDL default library path in VerificPass --- frontends/verific/verific.cc | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 5790e92f0..e366299d8 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3688,6 +3688,14 @@ struct VerificPass : public Pass { veri_file::AddLOption(args[++argidx].c_str()); continue; } + if (GetSize(args) > argidx && args[argidx] == "-set_vhdl_default_library_path") { + for (argidx++; argidx < GetSize(args); argidx++) { +#ifdef VERIFIC_VHDL_SUPPORT + vhdl_file::SetDefaultLibraryPath(args[argidx].c_str()); +#endif + } + goto check_error; + } #endif break; } From 2c5d79d441eac99b776631ab357fb06d52e1aca0 Mon Sep 17 00:00:00 2001 From: Dhaval Chaudhari Date: Sun, 4 Jan 2026 01:57:47 +0530 Subject: [PATCH 2/4] fix --- frontends/verific/verific.cc | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index e366299d8..56854b5ff 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3688,19 +3688,19 @@ struct VerificPass : public Pass { veri_file::AddLOption(args[++argidx].c_str()); continue; } - if (GetSize(args) > argidx && args[argidx] == "-set_vhdl_default_library_path") { - for (argidx++; argidx < GetSize(args); argidx++) { -#ifdef VERIFIC_VHDL_SUPPORT - vhdl_file::SetDefaultLibraryPath(args[argidx].c_str()); -#endif - } - goto check_error; - } #endif break; } #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT + if (GetSize(args) > argidx && args[argidx] == "-set_vhdl_default_library_path") { + for (argidx++; argidx < GetSize(args); argidx++) { + #ifdef VERIFIC_VHDL_SUPPORT + vhdl_file::SetDefaultLibraryPath(args[argidx].c_str()); + #endif + } + goto check_error; + } if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F")) { unsigned verilog_mode = veri_file::UNDEFINED; From 0f279eef41bb2791ebb01432688dfd7523442400 Mon Sep 17 00:00:00 2001 From: Dhaval Chaudhari Date: Sun, 4 Jan 2026 02:01:50 +0530 Subject: [PATCH 3/4] fix indentation --- frontends/verific/verific.cc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 56854b5ff..886c28093 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3695,9 +3695,9 @@ struct VerificPass : public Pass { #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (GetSize(args) > argidx && args[argidx] == "-set_vhdl_default_library_path") { for (argidx++; argidx < GetSize(args); argidx++) { - #ifdef VERIFIC_VHDL_SUPPORT +#ifdef VERIFIC_VHDL_SUPPORT vhdl_file::SetDefaultLibraryPath(args[argidx].c_str()); - #endif +#endif } goto check_error; } From e0ce4b42f6b3a4a5a1ac87892cfa24035aa78724 Mon Sep 17 00:00:00 2001 From: Dhaval Chaudhari Date: Mon, 5 Jan 2026 23:32:23 +0530 Subject: [PATCH 4/4] fix for VHDL default library path handling --- frontends/verific/verific.cc | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 886c28093..59ee7ea03 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3692,15 +3692,15 @@ struct VerificPass : public Pass { break; } -#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT - if (GetSize(args) > argidx && args[argidx] == "-set_vhdl_default_library_path") { - for (argidx++; argidx < GetSize(args); argidx++) { #ifdef VERIFIC_VHDL_SUPPORT + if (GetSize(args) > argidx && args[argidx] == "-set_vhdl_default_library_path") { + for (argidx++; argidx < GetSize(args); argidx++) vhdl_file::SetDefaultLibraryPath(args[argidx].c_str()); -#endif - } goto check_error; } +#endif + +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT if (GetSize(args) > argidx && (args[argidx] == "-f" || args[argidx] == "-F")) { unsigned verilog_mode = veri_file::UNDEFINED;