mirror of
https://github.com/YosysHQ/yosys
synced 2025-04-27 02:45:52 +00:00
Merge remote-tracking branch 'origin/master' into xaig
This commit is contained in:
Eddie Hung
commit
f7c7003a19
21 changed files with 280 additions and 129 deletions
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@ -140,6 +140,23 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
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}
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}
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// Return the "basic" type for an array item.
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std::string basic_cell_type(const std::string celltype, int pos[3] = nullptr) {
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std::string basicType = celltype;
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if (celltype.substr(0, 7) == "$array:") {
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int pos_idx = celltype.find_first_of(':');
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int pos_num = celltype.find_first_of(':', pos_idx + 1);
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int pos_type = celltype.find_first_of(':', pos_num + 1);
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basicType = celltype.substr(pos_type + 1);
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if (pos != nullptr) {
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pos[0] = pos_idx;
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pos[1] = pos_num;
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pos[2] = pos_type;
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}
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}
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return basicType;
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}
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bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check, bool flag_simcheck, std::vector<std::string> &libdirs)
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{
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bool did_something = false;
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@ -178,9 +195,11 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
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std::vector<RTLIL::SigSpec> connections_to_add_signal;
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if (cell->type.substr(0, 7) == "$array:") {
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int pos_idx = cell->type.str().find_first_of(':');
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int pos_num = cell->type.str().find_first_of(':', pos_idx + 1);
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int pos_type = cell->type.str().find_first_of(':', pos_num + 1);
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int pos[3];
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basic_cell_type(cell->type.str(), pos);
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int pos_idx = pos[0];
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int pos_num = pos[1];
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int pos_type = pos[2];
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int idx = atoi(cell->type.str().substr(pos_idx + 1, pos_num).c_str());
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int num = atoi(cell->type.str().substr(pos_num + 1, pos_type).c_str());
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array_cells[cell] = std::pair<int, int>(idx, num);
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@ -439,10 +458,7 @@ void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*, IdString::
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for (auto cell : mod->cells()) {
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std::string celltype = cell->type.str();
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if (celltype.substr(0, 7) == "$array:") {
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int pos_idx = celltype.find_first_of(':');
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int pos_num = celltype.find_first_of(':', pos_idx + 1);
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int pos_type = celltype.find_first_of(':', pos_num + 1);
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celltype = celltype.substr(pos_type + 1);
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celltype = basic_cell_type(celltype);
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}
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if (design->module(celltype))
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hierarchy_worker(design, used, design->module(celltype), indent+4);
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@ -502,9 +518,19 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)
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if (db.count(module) == 0) {
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int score = 0;
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db[module] = 0;
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for (auto cell : module->cells())
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if (design->module(cell->type))
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score = max(score, find_top_mod_score(design, design->module(cell->type), db) + 1);
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for (auto cell : module->cells()) {
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std::string celltype = cell->type.str();
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// Is this an array instance
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if (celltype.substr(0, 7) == "$array:") {
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celltype = basic_cell_type(celltype);
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}
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// Is this cell a module instance?
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auto instModule = design->module(celltype);
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// If there is no instance for this, issue a warning.
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if (instModule != nullptr) {
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score = max(score, find_top_mod_score(design, instModule, db) + 1);
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}
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}
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db[module] = score;
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}
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return db.at(module);
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@ -195,6 +195,13 @@ struct WreduceWorker
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for (auto bit : sig_q)
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work_queue_bits.insert(bit);
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// Narrow ARST_VALUE parameter to new size.
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if (cell->parameters.count("\\ARST_VALUE")) {
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Const arst_value = cell->getParam("\\ARST_VALUE");
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arst_value.bits.resize(GetSize(sig_q));
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cell->setParam("\\ARST_VALUE", arst_value);
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}
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cell->setPort("\\D", sig_d);
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cell->setPort("\\Q", sig_q);
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cell->fixup_parameters();
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@ -327,8 +327,26 @@ void extract_cell(RTLIL::Cell *cell, bool keepff)
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}
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}
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std::string remap_name(RTLIL::IdString abc_name)
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std::string remap_name(RTLIL::IdString abc_name, RTLIL::Wire **orig_wire = nullptr)
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{
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std::string abc_sname = abc_name.substr(1);
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if (abc_sname.substr(0, 5) == "ys__n") {
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int sid = std::stoi(abc_sname.substr(5));
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bool inv = abc_sname.back() == 'v';
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for (auto sig : signal_list) {
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if (sig.id == sid && sig.bit.wire != nullptr) {
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std::stringstream sstr;
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sstr << "$abc$" << map_autoidx << "$" << sig.bit.wire->name.substr(1);
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if (sig.bit.wire->width != 1)
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sstr << "[" << sig.bit.offset << "]";
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if (inv)
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sstr << "_inv";
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if (orig_wire != nullptr)
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*orig_wire = sig.bit.wire;
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return sstr.str();
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}
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}
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}
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std::stringstream sstr;
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sstr << "$abc$" << map_autoidx << "$" << abc_name.substr(1);
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return sstr.str();
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@ -353,12 +371,12 @@ void dump_loop_graph(FILE *f, int &nr, std::map<int, std::set<int>> &edges, std:
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}
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for (auto n : nodes)
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fprintf(f, " n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit),
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fprintf(f, " ys__n%d [label=\"%s\\nid=%d, count=%d\"%s];\n", n, log_signal(signal_list[n].bit),
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n, in_counts[n], workpool.count(n) ? ", shape=box" : "");
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for (auto &e : edges)
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for (auto n : e.second)
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fprintf(f, " n%d -> n%d;\n", e.first, n);
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fprintf(f, " ys__n%d -> ys__n%d;\n", e.first, n);
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fprintf(f, "}\n");
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}
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@ -624,7 +642,7 @@ struct abc_output_filter
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void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::string script_file, std::string exe_file,
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std::string liberty_file, std::string constr_file, bool cleanup, vector<int> lut_costs, bool dff_mode, std::string clk_str,
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bool keepff, std::string delay_target, std::string sop_inputs, std::string sop_products, std::string lutin_shared, bool fast_mode,
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const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode)
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const std::vector<RTLIL::Cell*> &cells, bool show_tempdir, bool sop_mode, bool abc_dress)
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{
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module = current_module;
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map_autoidx = autoidx++;
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@ -728,7 +746,8 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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for (size_t pos = abc_script.find("{S}"); pos != std::string::npos; pos = abc_script.find("{S}", pos))
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abc_script = abc_script.substr(0, pos) + lutin_shared + abc_script.substr(pos+3);
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if (abc_dress)
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abc_script += "; dress";
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abc_script += stringf("; write_blif %s/output.blif", tempdir_name.c_str());
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abc_script = add_echos_to_abc_cmd(abc_script);
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@ -784,7 +803,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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for (auto &si : signal_list) {
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if (!si.is_port || si.type != G(NONE))
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continue;
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fprintf(f, " n%d", si.id);
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fprintf(f, " ys__n%d", si.id);
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pi_map[count_input++] = log_signal(si.bit);
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}
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if (count_input == 0)
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@ -796,17 +815,17 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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for (auto &si : signal_list) {
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if (!si.is_port || si.type == G(NONE))
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continue;
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fprintf(f, " n%d", si.id);
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fprintf(f, " ys__n%d", si.id);
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po_map[count_output++] = log_signal(si.bit);
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}
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fprintf(f, "\n");
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for (auto &si : signal_list)
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fprintf(f, "# n%-5d %s\n", si.id, log_signal(si.bit));
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fprintf(f, "# ys__n%-5d %s\n", si.id, log_signal(si.bit));
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for (auto &si : signal_list) {
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if (si.bit.wire == NULL) {
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fprintf(f, ".names n%d\n", si.id);
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fprintf(f, ".names ys__n%d\n", si.id);
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if (si.bit == RTLIL::State::S1)
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fprintf(f, "1\n");
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}
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@ -815,68 +834,68 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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int count_gates = 0;
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for (auto &si : signal_list) {
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if (si.type == G(BUF)) {
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fprintf(f, ".names n%d n%d\n", si.in1, si.id);
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fprintf(f, ".names ys__n%d ys__n%d\n", si.in1, si.id);
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fprintf(f, "1 1\n");
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} else if (si.type == G(NOT)) {
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fprintf(f, ".names n%d n%d\n", si.in1, si.id);
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fprintf(f, ".names ys__n%d ys__n%d\n", si.in1, si.id);
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fprintf(f, "0 1\n");
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} else if (si.type == G(AND)) {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "11 1\n");
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} else if (si.type == G(NAND)) {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "0- 1\n");
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fprintf(f, "-0 1\n");
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} else if (si.type == G(OR)) {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "-1 1\n");
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fprintf(f, "1- 1\n");
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} else if (si.type == G(NOR)) {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "00 1\n");
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} else if (si.type == G(XOR)) {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "01 1\n");
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fprintf(f, "10 1\n");
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} else if (si.type == G(XNOR)) {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "00 1\n");
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fprintf(f, "11 1\n");
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} else if (si.type == G(ANDNOT)) {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "10 1\n");
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} else if (si.type == G(ORNOT)) {
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fprintf(f, ".names n%d n%d n%d\n", si.in1, si.in2, si.id);
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fprintf(f, ".names ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.id);
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fprintf(f, "1- 1\n");
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fprintf(f, "-0 1\n");
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} else if (si.type == G(MUX)) {
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fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
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fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
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fprintf(f, "1-0 1\n");
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fprintf(f, "-11 1\n");
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} else if (si.type == G(AOI3)) {
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fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
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fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
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fprintf(f, "-00 1\n");
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fprintf(f, "0-0 1\n");
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} else if (si.type == G(OAI3)) {
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fprintf(f, ".names n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.id);
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fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.id);
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fprintf(f, "00- 1\n");
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fprintf(f, "--0 1\n");
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} else if (si.type == G(AOI4)) {
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fprintf(f, ".names n%d n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
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fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
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fprintf(f, "-0-0 1\n");
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fprintf(f, "-00- 1\n");
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fprintf(f, "0--0 1\n");
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fprintf(f, "0-0- 1\n");
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} else if (si.type == G(OAI4)) {
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fprintf(f, ".names n%d n%d n%d n%d n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
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fprintf(f, ".names ys__n%d ys__n%d ys__n%d ys__n%d ys__n%d\n", si.in1, si.in2, si.in3, si.in4, si.id);
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fprintf(f, "00-- 1\n");
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fprintf(f, "--00 1\n");
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} else if (si.type == G(FF)) {
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if (si.init == State::S0 || si.init == State::S1) {
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fprintf(f, ".latch n%d n%d %d\n", si.in1, si.id, si.init == State::S1 ? 1 : 0);
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fprintf(f, ".latch ys__n%d ys__n%d %d\n", si.in1, si.id, si.init == State::S1 ? 1 : 0);
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recover_init = true;
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} else
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fprintf(f, ".latch n%d n%d 2\n", si.in1, si.id);
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fprintf(f, ".latch ys__n%d ys__n%d 2\n", si.in1, si.id);
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} else if (si.type != G(NONE))
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log_abort();
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if (si.type != G(NONE))
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|
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@ -889,7 +908,6 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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log("Extracted %d gates and %d wires to a netlist network with %d inputs and %d outputs.\n",
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count_gates, GetSize(signal_list), count_input, count_output);
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log_push();
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if (count_output > 0)
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{
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log_header(design, "Executing ABC.\n");
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@ -988,7 +1006,10 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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log_error("ABC output file does not contain a module `netlist'.\n");
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for (auto &it : mapped_mod->wires_) {
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RTLIL::Wire *w = it.second;
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RTLIL::Wire *wire = module->addWire(remap_name(w->name));
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RTLIL::Wire *orig_wire = nullptr;
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RTLIL::Wire *wire = module->addWire(remap_name(w->name, &orig_wire));
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if (orig_wire != nullptr && orig_wire->attributes.count("\\src"))
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wire->attributes["\\src"] = orig_wire->attributes["\\src"];
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if (markgroups) wire->attributes["\\abcgroup"] = map_autoidx;
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design->select(module, wire);
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}
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@ -1213,7 +1234,7 @@ void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std::strin
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for (auto &si : signal_list)
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if (si.is_port) {
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char buffer[100];
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snprintf(buffer, 100, "\\n%d", si.id);
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snprintf(buffer, 100, "\\ys__n%d", si.id);
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RTLIL::SigSig conn;
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if (si.type != G(NONE)) {
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conn.first = si.bit;
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|
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@ -1407,6 +1428,11 @@ struct AbcPass : public Pass {
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log(" this attribute is a unique integer for each ABC process started. This\n");
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log(" is useful for debugging the partitioning of clock domains.\n");
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log("\n");
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log(" -dress\n");
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log(" run the 'dress' command after all other ABC commands. This aims to\n");
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log(" preserve naming by an equivalence check between the original and post-ABC\n");
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log(" netlists (experimental).\n");
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log("\n");
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log("When neither -liberty nor -lut is used, the Yosys standard cell library is\n");
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log("loaded into ABC before the ABC script is executed.\n");
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log("\n");
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@ -1441,6 +1467,7 @@ struct AbcPass : public Pass {
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std::string delay_target, sop_inputs, sop_products, lutin_shared = "-S 1";
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bool fast_mode = false, dff_mode = false, keepff = false, cleanup = true;
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bool show_tempdir = false, sop_mode = false;
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bool abc_dress = false;
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vector<int> lut_costs;
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||||
markgroups = false;
|
||||
|
||||
|
|
@ -1555,6 +1582,10 @@ struct AbcPass : public Pass {
|
|||
map_mux16 = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-dress") {
|
||||
abc_dress = true;
|
||||
continue;
|
||||
}
|
||||
if (arg == "-g" && argidx+1 < args.size()) {
|
||||
for (auto g : split_tokens(args[++argidx], ",")) {
|
||||
vector<string> gate_list;
|
||||
|
|
@ -1704,7 +1735,7 @@ struct AbcPass : public Pass {
|
|||
|
||||
if (!dff_mode || !clk_str.empty()) {
|
||||
abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, dff_mode, clk_str, keepff,
|
||||
delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode);
|
||||
delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, mod->selected_cells(), show_tempdir, sop_mode, abc_dress);
|
||||
continue;
|
||||
}
|
||||
|
||||
|
|
@ -1849,7 +1880,7 @@ struct AbcPass : public Pass {
|
|||
en_polarity = std::get<2>(it.first);
|
||||
en_sig = assign_map(std::get<3>(it.first));
|
||||
abc_module(design, mod, script_file, exe_file, liberty_file, constr_file, cleanup, lut_costs, !clk_sig.empty(), "$",
|
||||
keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode);
|
||||
keepff, delay_target, sop_inputs, sop_products, lutin_shared, fast_mode, it.second, show_tempdir, sop_mode, abc_dress);
|
||||
assign_map.set(mod);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -660,8 +660,8 @@ struct DfflibmapPass : public Pass {
|
|||
map_adff_to_dff("$_DFF_PP0_", "$_DFF_P_");
|
||||
map_adff_to_dff("$_DFF_PP1_", "$_DFF_P_");
|
||||
|
||||
log(" final dff cell mappings:\n");
|
||||
logmap_all();
|
||||
log(" final dff cell mappings:\n");
|
||||
logmap_all();
|
||||
|
||||
for (auto &it : design->modules_)
|
||||
if (design->selected(it.second) && !it.second->get_bool_attribute("\\blackbox"))
|
||||
|
|
|
|||
|
|
@ -132,9 +132,9 @@ static void dump_dot_graph(string filename,
|
|||
pool<RTLIL::SigBit> nodes, dict<RTLIL::SigBit, pool<RTLIL::SigBit>> edges,
|
||||
pool<RTLIL::SigBit> inputs, pool<RTLIL::SigBit> outputs,
|
||||
std::function<GraphStyle(RTLIL::SigBit)> node_style =
|
||||
[](RTLIL::SigBit) { return GraphStyle{}; },
|
||||
[](RTLIL::SigBit) { return GraphStyle{}; },
|
||||
std::function<GraphStyle(RTLIL::SigBit, RTLIL::SigBit)> edge_style =
|
||||
[](RTLIL::SigBit, RTLIL::SigBit) { return GraphStyle{}; },
|
||||
[](RTLIL::SigBit, RTLIL::SigBit) { return GraphStyle{}; },
|
||||
string name = "")
|
||||
{
|
||||
FILE *f = fopen(filename.c_str(), "w");
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue