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Merge remote-tracking branch 'origin/master' into xaig

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This commit is contained in:
Eddie Hung 2019-06-12 08:50:39 -07:00
commit f7a9769c14
140 changed files with 4698 additions and 1852 deletions
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23
tests/tools/autotest.sh
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@ -89,6 +89,13 @@ done
compile_and_run() {
exe="$1"; output="$2"; shift 2
ext=${1##*.}
if [ "$ext" == "sv" ]; then
language_gen="-g2012"
else
language_gen="-g2005"
fi
if $use_modelsim; then
altver=$( ls -v /opt/altera/ | grep '^[0-9]' | tail -n1; )
/opt/altera/$altver/modelsim_ase/bin/vlib work
@ -99,7 +106,7 @@ compile_and_run() {
/opt/Xilinx/Vivado/$xilver/bin/xvlog $xinclude_opts -d outfile=\"$output\" "$@"
/opt/Xilinx/Vivado/$xilver/bin/xelab -R work.testbench
else
iverilog $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
iverilog $language_gen $include_opts -Doutfile=\"$output\" -s testbench -o "$exe" "$@"
vvp -n "$exe"
fi
}
@ -110,7 +117,7 @@ for fn
do
bn=${fn%.*}
ext=${fn##*.}
if [[ "$ext" != "v" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
if [[ "$ext" != "v" ]] && [[ "$ext" != "sv" ]] && [[ "$ext" != "aag" ]] && [[ "$ext" != "aig" ]]; then
echo "Invalid argument: $fn" >&2
exit 1
fi
@ -123,6 +130,10 @@ do
echo -n "Test: $bn "
fi
if [ "$ext" == sv ]; then
frontend="$frontend -sv"
fi
rm -f ${bn}.{err,log,skip}
mkdir -p ${bn}.out
rm -rf ${bn}.out/*
@ -134,9 +145,10 @@ do
if [[ "$ext" == "v" ]]; then
egrep -v '^\s*`timescale' ../$fn > ${bn}_ref.${ext}
elif [[ "$ext" == "aig" ]] || [[ "$ext" == "aag" ]]; then
"$toolsdir"/../../yosys-abc -c "read_aiger ../${fn}; write ${bn}_ref.v"
else
"$toolsdir"/../../yosys -f "$frontend $include_opts" -b "verilog" -o ${bn}_ref.v ../${fn}
frontend="verilog -noblackbox"
cp ../${fn} ${bn}_ref.${ext}
fi
rm -f ${bn}_ref.fir
@ -147,7 +159,8 @@ do
fi
if $genvcd; then sed -i 's,// \$dump,$dump,g' ${bn}_tb.v; fi
compile_and_run ${bn}_tb_ref ${bn}_out_ref ${bn}_tb.v ${bn}_ref.v $libs \
"$toolsdir"/../../techlibs/common/simlib.v
"$toolsdir"/../../techlibs/common/simlib.v \
"$toolsdir"/../../techlibs/common/simcells.v
if $genvcd; then mv testbench.vcd ${bn}_ref.vcd; fi
test_count=0