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Merge pull request #5089 from YosysHQ/krys/cutpoint_whole

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cutpoint: Re-add whole module optimization
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KrystalDelusion 2025-05-16 09:22:28 +12:00 • committed by GitHub
commit f7888c607b
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14
passes/sat/cutpoint.cc
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@ -86,6 +86,20 @@ struct CutpointPass : public Pass {
for (auto module : design->all_selected_modules())
{
if (module->is_selected_whole()) {
log("Making all outputs of module %s cut points, removing module contents.\n", log_id(module));
module->new_connections(std::vector<RTLIL::SigSig>());
for (auto cell : vector<Cell*>(module->cells()))
module->remove(cell);
vector<Wire*> output_wires;
for (auto wire : module->wires())
if (wire->port_output)
output_wires.push_back(wire);
for (auto wire : output_wires)
module->connect(wire, flag_undef ? Const(State::Sx, GetSize(wire)) : module->Anyseq(NEW_ID, GetSize(wire)));
continue;
}
SigMap sigmap(module);
pool<SigBit> cutpoint_bits;