From f76fd9280b54bd40a56c5eb47fb411eeb3714673 Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Fri, 14 Feb 2025 06:56:20 -0800 Subject: [PATCH] Clean up Verific --- frontends/verific/verific.cc | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 55bc9c9f8..b635518b7 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1007,9 +1007,8 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr Net *net_a_msb = inst->GetInput1Bit(0); if (net_cin->IsGnd()) cell = module->addShr(inst_name, IN1, IN2, OUT, false); - else if (net_cin == net_a_msb) { + else if (net_cin == net_a_msb) cell = module->addSshr(inst_name, IN1, IN2, OUT, true); - } else log_error("Can't import Verific OPER_SHIFT_RIGHT instance %s: carry_in is neither 0 nor msb of left input\n", inst->Name()); import_attributes(cell->attributes, inst); @@ -3167,7 +3166,7 @@ struct VerificPass : public Pass { { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| log("\n"); - #ifdef VERIFIC_SYSTEMVERILOG_SUPPORT +#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT log(" verific {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv} ..\n"); log("\n"); log("Load the specified Verilog/SystemVerilog files into Verific.\n");