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write_verilog: don't dump single_bit_vector attribute

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Emil J. Tywoniak 2025-05-12 13:36:25 +02:00
parent e5171d6aa1
commit f73c6a9c9a
1 changed files with 1 additions and 0 deletions
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1
backends/verilog/verilog_backend.cc
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@ -383,6 +383,7 @@ void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString,
if (attr2comment)
as_comment = true;
for (auto it = attributes.begin(); it != attributes.end(); ++it) {
if (it->first == ID::single_bit_vector) continue;
if (it->first == ID::init && regattr) continue;
f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str());
f << stringf(" = ");