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Remove auto_wire framework (smarter than the verilog standard)

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This commit is contained in:
Clifford Wolf 2013-11-24 17:29:11 +01:00
parent 609caa23b5
commit f71e27dbf1
9 changed files with 5 additions and 126 deletions
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10
frontends/ast/genrtlil.cc
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@ -917,15 +917,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
RTLIL::Wire *wire = new RTLIL::Wire;
wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
wire->name = str;
if (width_hint >= 0) {
wire->width = width_hint;
log("Warning: Identifier `%s' is implicitly declared with width %d at %s:%d.\n",
str.c_str(), width_hint, filename.c_str(), linenum);
} else {
log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n",
str.c_str(), filename.c_str(), linenum);
}
wire->auto_width = true;
log("Warning: Identifier `%s' is implicitly declared at %s:%d.\n", str.c_str(), filename.c_str(), linenum);
current_module->wires[str] = wire;
}
else if (id2ast->type == AST_PARAMETER || id2ast->type == AST_LOCALPARAM) {