From f70a66f5b3bf8e66e5ffc49ce9050c8609a3ba64 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Thu, 5 Sep 2024 16:20:13 +1200
Subject: [PATCH] Docs: Assert cell has group

Explicitly assign $_TBUF_ to `gate_other` and remove catch if a cell has no group.
---
 docs/source/cell_word.rst   | 2 --
 techlibs/common/cellhelp.py | 7 +------
 techlibs/common/simcells.v  | 1 +
 3 files changed, 2 insertions(+), 8 deletions(-)

diff --git a/docs/source/cell_word.rst b/docs/source/cell_word.rst
index bfb14f510..d52c4c934 100644
--- a/docs/source/cell_word.rst
+++ b/docs/source/cell_word.rst
@@ -28,5 +28,3 @@ Simulation models for the RTL cells can be found in the file
    /cell/word_formal
    /cell/word_debug
    /cell/word_wire
-
-.. todo:: Add check for unexpected ``word_other`` cells
diff --git a/techlibs/common/cellhelp.py b/techlibs/common/cellhelp.py
index 9aa3def93..a6b2ce88a 100644
--- a/techlibs/common/cellhelp.py
+++ b/techlibs/common/cellhelp.py
@@ -88,12 +88,7 @@ for line in fileinput.input():
             simHelper.desc.pop(1)
 
         # check group
-        if not simHelper.group:
-            if short_filename == 'simcells.v':
-                simHelper.group = "gate_"
-            elif short_filename == 'simlib.v':
-                simHelper.group = "word_"
-            simHelper.group += "other"
+        assert simHelper.group, f"techlibs/common/{simHelper.source}: {simHelper.name} cell missing group"
 
         # dump
         print(simHelper)
diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v
index 104022079..1a113447e 100644
--- a/techlibs/common/simcells.v
+++ b/techlibs/common/simcells.v
@@ -461,6 +461,7 @@ endmodule
 //  |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 //-
 //-     $_TBUF_ (A, E, Y)
+//* group gate_other
 //-
 //- A tri-state buffer.
 //-