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sim: -hdlname option to preserve flattened hierarchy in sim output

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This commit is contained in:
Jannis Harder 2022-08-09 15:43:26 +02:00
parent 66f761a8c5
commit f7023d06a2
2 changed files with 43 additions and 9 deletions
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@ -9,6 +9,8 @@ Yosys 0.20 .. Yosys 0.20-dev
- Added option "-formal" to "memory_map" pass
- Added option "-witness" to "rename" - give public names to all signals
present in yosys witness traces
- Added option "-hdlname" to "sim" pass - preserves hiearachy when writing
simulation output for a flattened design
* Formal Verification
- Added $anyinit cell to directly represent FFs with an unconstrained