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https://github.com/YosysHQ/yosys
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cxxrtl: generate debug information for non-localized public wires.
Debug information describes values, wires, and memories with a simple C-compatible layout. It can be emitted on demand into a map, which has no runtime cost when it is unused, and allows late bound designs. The `hdlname` attribute is used as the lookup key such that original names, as emitted by the frontend, can be used for debugging and introspection.
This commit is contained in:
whitequark
parent
784bfec67c
commit
f6e16e7f4c
2 changed files with 131 additions and 2 deletions
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@ -502,6 +502,15 @@ std::string escape_cxx_string(const std::string &input)
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return output;
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}
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template<class T>
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std::string get_hdl_name(T *object)
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{
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if (object->has_attribute(ID::hdlname))
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return object->get_string_attribute(ID::hdlname);
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else
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return object->name.str();
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}
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struct CxxrtlWorker {
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bool split_intf = false;
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std::string intf_filename;
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@ -516,6 +525,8 @@ struct CxxrtlWorker {
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bool run_proc_flatten = false;
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bool max_opt_level = false;
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bool debug_info = false;
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std::ostringstream f;
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std::string indent;
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int temporary = 0;
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@ -1593,6 +1604,34 @@ struct CxxrtlWorker {
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dec_indent();
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}
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void dump_debug_info_method(RTLIL::Module *module)
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{
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inc_indent();
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f << indent << "assert(path.empty() || path[path.size() - 1] == ' ');\n";
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for (auto wire : module->wires()) {
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if (wire->name[0] != '\\')
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continue;
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if (localized_wires.count(wire))
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continue;
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f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(wire));
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f << ", debug_item(" << mangle(wire) << "));\n";
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}
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for (auto &memory_it : module->memories) {
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if (memory_it.first[0] != '\\')
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continue;
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f << indent << "items.emplace(path + " << escape_cxx_string(get_hdl_name(memory_it.second));
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f << ", debug_item(" << mangle(memory_it.second) << "));\n";
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}
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for (auto cell : module->cells()) {
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if (is_internal_cell(cell->type))
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continue;
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const char *access = is_cxxrtl_blackbox_cell(cell) ? "->" : ".";
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f << indent << mangle(cell) << access << "debug_info(items, ";
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f << "path + " << escape_cxx_string(get_hdl_name(cell) + ' ') << ");\n";
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}
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dec_indent();
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}
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void dump_metadata_map(const dict<RTLIL::IdString, RTLIL::Const> &metadata_map)
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{
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if (metadata_map.empty()) {
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@ -1641,6 +1680,12 @@ struct CxxrtlWorker {
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dump_commit_method(module);
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f << indent << "}\n";
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f << "\n";
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if (debug_info) {
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f << indent << "void debug_info(debug_items &items, std::string path = \"\") override {\n";
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dump_debug_info_method(module);
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f << indent << "}\n";
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f << "\n";
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}
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f << indent << "static std::unique_ptr<" << mangle(module);
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f << template_params(module, /*is_decl=*/false) << "> ";
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f << "create(std::string name, metadata_map parameters, metadata_map attributes);\n";
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@ -1689,7 +1734,7 @@ struct CxxrtlWorker {
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if (cell_module->get_bool_attribute(ID(cxxrtl_blackbox))) {
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f << indent << "std::unique_ptr<" << mangle(cell_module) << template_args(cell) << "> ";
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f << mangle(cell) << " = " << mangle(cell_module) << template_args(cell);
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f << "::create(" << escape_cxx_string(cell->name.str()) << ", ";
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f << "::create(" << escape_cxx_string(get_hdl_name(cell)) << ", ";
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dump_metadata_map(cell->parameters);
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f << ", ";
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dump_metadata_map(cell->attributes);
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@ -1703,6 +1748,8 @@ struct CxxrtlWorker {
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f << "\n";
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f << indent << "bool eval() override;\n";
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f << indent << "bool commit() override;\n";
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if (debug_info)
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f << indent << "void debug_info(debug_items &items, std::string path = \"\") override;\n";
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dec_indent();
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f << indent << "}; // struct " << mangle(module) << "\n";
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f << "\n";
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@ -1721,6 +1768,12 @@ struct CxxrtlWorker {
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dump_commit_method(module);
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f << indent << "}\n";
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f << "\n";
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if (debug_info) {
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f << indent << "void " << mangle(module) << "::debug_info(debug_items &items, std::string path) {\n";
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dump_debug_info_method(module);
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f << indent << "}\n";
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f << "\n";
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}
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}
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void dump_design(RTLIL::Design *design)
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@ -2120,6 +2173,7 @@ struct CxxrtlWorker {
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struct CxxrtlBackend : public Backend {
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static const int DEFAULT_OPT_LEVEL = 5;
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static const int DEFAULT_DEBUG_LEVEL = 1;
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CxxrtlBackend() : Backend("cxxrtl", "convert design to C++ RTL simulation") { }
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void help() YS_OVERRIDE
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@ -2313,10 +2367,22 @@ struct CxxrtlBackend : public Backend {
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log(" -O5\n");
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log(" like -O4, and run `proc; flatten` first.\n");
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log("\n");
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log(" -g <level>\n");
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log(" set the debug level. the default is -g%d. higher debug levels provide\n", DEFAULT_DEBUG_LEVEL);
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log(" more visibility and generate more code, but do not pessimize evaluation.\n");
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log("\n");
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log(" -g0\n");
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log(" no debug information.\n");
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log("\n");
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log(" -g1\n");
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log(" debug information for non-localized public wires.\n");
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log("\n");
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}
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void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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int opt_level = DEFAULT_OPT_LEVEL;
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int debug_level = DEFAULT_DEBUG_LEVEL;
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CxxrtlWorker worker;
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log_header(design, "Executing CXXRTL backend.\n");
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@ -2332,6 +2398,14 @@ struct CxxrtlBackend : public Backend {
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opt_level = std::stoi(args[argidx].substr(2));
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continue;
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}
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if (args[argidx] == "-g" && argidx+1 < args.size()) {
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debug_level = std::stoi(args[++argidx]);
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continue;
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}
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if (args[argidx].substr(0, 2) == "-g" && args[argidx].size() == 3 && isdigit(args[argidx][2])) {
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debug_level = std::stoi(args[argidx].substr(2));
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continue;
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}
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if (args[argidx] == "-header") {
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worker.split_intf = true;
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continue;
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@ -2368,6 +2442,17 @@ struct CxxrtlBackend : public Backend {
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log_cmd_error("Invalid optimization level %d.\n", opt_level);
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}
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switch (debug_level) {
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// the highest level here must match DEFAULT_DEBUG_LEVEL
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case 1:
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worker.debug_info = true;
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YS_FALLTHROUGH
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case 0:
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break;
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default:
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log_cmd_error("Invalid optimization level %d.\n", opt_level);
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}
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std::ofstream intf_f;
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if (worker.split_intf) {
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if (filename == "<stdout>")
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@ -49,6 +49,8 @@ namespace cxxrtl {
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// invisible to the compiler, (b) we often operate on non-power-of-2 values and have to clear the high bits anyway.
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// Therefore, using relatively wide chunks and clearing the high bits explicitly and only when we know they may be
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// clobbered results in simpler generated code.
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typedef uint32_t chunk_t;
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template<typename T>
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struct chunk_traits {
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static_assert(std::is_integral<T>::value && std::is_unsigned<T>::value,
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@ -65,7 +67,7 @@ template<size_t Bits>
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struct value : public expr_base<value<Bits>> {
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static constexpr size_t bits = Bits;
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using chunk = chunk_traits<uint32_t>;
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using chunk = chunk_traits<chunk_t>;
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static constexpr chunk::type msb_mask = (Bits % chunk::bits == 0) ? chunk::mask
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: chunk::mask >> (chunk::bits - (Bits % chunk::bits));
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@ -712,6 +714,46 @@ struct metadata {
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typedef std::map<std::string, metadata> metadata_map;
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// This structure is intended for consumption via foreign function interfaces, like Python's ctypes.
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// Because of this it uses a C-style layout that is easy to parse rather than more idiomatic C++.
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struct debug_item {
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enum : uint32_t {
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VALUE = 0,
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WIRE = 1,
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MEMORY = 2,
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} type;
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size_t width; // in bits
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size_t depth; // 1 if `type != MEMORY`
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chunk_t *curr;
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chunk_t *next; // nullptr if `type == VALUE || type == MEMORY`
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template<size_t Bits>
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debug_item(value<Bits> &item) : type(VALUE), width(Bits), depth(1),
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curr(item.data), next(nullptr) {
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static_assert(sizeof(item) == value<Bits>::chunks * sizeof(chunk_t),
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"value<Bits> is not compatible with C layout");
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}
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template<size_t Bits>
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debug_item(wire<Bits> &item) : type(WIRE), width(Bits), depth(1),
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curr(item.curr.data), next(item.next.data) {
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static_assert(sizeof(item.curr) == value<Bits>::chunks * sizeof(chunk_t) &&
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sizeof(item.next) == value<Bits>::chunks * sizeof(chunk_t),
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"wire<Bits> is not compatible with C layout");
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}
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template<size_t Width>
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debug_item(memory<Width> &item) : type(MEMORY), width(Width), depth(item.data.size()),
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curr(item.data.empty() ? nullptr : item.data[0].data), next(nullptr) {
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static_assert(sizeof(item.data[0]) == value<Width>::chunks * sizeof(chunk_t),
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"memory<Width> is not compatible with C layout");
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}
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};
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static_assert(std::is_standard_layout<debug_item>::value, "debug_item is not compatible with C layout");
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typedef std::map<std::string, debug_item> debug_items;
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struct module {
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module() {}
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virtual ~module() {}
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@ -731,6 +773,8 @@ struct module {
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} while (commit() && !converged);
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return deltas;
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}
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virtual void debug_info(debug_items &items, std::string path = "") {}
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};
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} // namespace cxxrtl
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