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Allow blocks with declarations within constant functions

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This commit is contained in:
Zachary Snow 2020-07-25 10:16:12 -06:00
parent dafe04d559
commit f69daf4830
3 changed files with 45 additions and 18 deletions
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23
tests/various/const_func_block_var.v Normal file
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module top(out);
function integer operation;
input integer num;
begin
operation = 0;
begin : op_i
integer i;
for (i = 0; i < 2; i = i + 1)
begin : op_j
integer j;
for (j = i; j < i * 2; j = j + 1)
num = num + 1;
end
num = num * 2;
end
operation = num;
end
endfunction
localparam res = operation(4);
output wire [31:0] out;
assign out = res;
endmodule

1
tests/various/const_func_block_var.ys Normal file
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read_verilog const_func_block_var.v